Manil Gomony

Application Specific Integrated Circuit Lab

CMOS scaling is approaching its physical limit and processing demands are ever increasing. Our aim is to design cross-stack optimizations to push the boundaries of what is physically possible.

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Research Profile

CMOS scaling is approaching its physical limit and processing demands are ever increasing. To keep the energy consumption and silicon area usage within the budget, the ASIC lab focuses its research on optimizations at different levels of design stack from applications, architecture, micro-architecture, logic, circuit, device and technology.

Meet some of our Researchers

Assistant Professor

Manil Dev Gomony

Recent Publications

Our most recent peer reviewed publications

Contact

  • Visiting address

    Flux, room 4.130
    Groene Loper 19
    5612 AP Eindhoven
    Netherlands

  • Postal address

    Department of Electrical Engineering
    P.O. Box 513
    5600 MB Eindhoven
    Netherlands

  • Teamlead